Prior art read only storage FET arrays are comprised of rectilinear arrangements of field effect transistors whose gates are connected in column to a word line and whose drains are connected for example to a reference potential and whose sources, for example, are connected in rows to bit sense lines. The array is programmed for a particular bit configuration by selectively deleting the gate connection for selected ones of the array FET devices so that the remaining devices embody the information desired to be stored. The techniques for disconnecting the selected gates from the word lines include the mask programmable technique of growing a thick oxide in the gate region for the selected FET device or, at a later stage in the processing, selectively etching away the gate connection for the FET device or alternately, severing the connection between the gate of the FET device and the word line by electrically fusing the connection with a high current or by melting the connection with the application of a laser beam.
Experience has shown that static electric charges accumulate on the gate and its lead due to handling prior to the cutting operation and to become isolated at the gate after the gate lead is cut. This produces an unpredictable conduction state for the array FET device instead of a solid off-state as is desired. The severity of this problem is a function of the integrity of the insulation layer between the gate and the substrate at the selected FET array device whose gate has been so severed. If the gate insulator has a very high resistivity, very little charge leakage will occur between the accumulated charge on the gate and the substrate and therefore the unpredictable conduction state for the FET array device will remain in effect for a substantial period of time, possibly for months or even years. The network effect of such a charge accumulation on a severed gate is that when the bit line is interrogated by the sense amplifiers for the array, an erroneous conduction state will be detected.
Various attempts have been made in the prior art to minimize the problem of residual charge accumulation on the gate of a severed gate FET array device, but no satisfactory solution has been offered to date. For example, Deliduka, et al. has disclosed in the IBM Technical Disclosure Bulletin, September 1976, page 1161 shows a monolithic integrated circuit fuse link wherein the integrated circuit is subjected to handling during the course of fabrication and, to protect the circuit from electrostatic charges, a protective diode is connected to the circuit by means of a fuse link. After handling is finished, the fuse link is severed. The fuse link then separates the protective diode from the circuit to be protected and thus the operation as disclosed by Deliduka does not provide for the participation of any accumulated charge on the integrated circuit after the circuit has been severed.
Other physical phenomena will inadvertently introduce charge to the severed gate of an FET array device so as to give an unpredictable conduction state for that device. For example, photoelectric charging by virtue of exposing the severed gate to ambient light will cause the conduction state for the device to change. Furthermore, ionic contamination from inadvertently introduced sodium ions, for example, will cause the gradual electrostatic charging of the severed gate, thereby producing an unpredictable conduction state for the FET array device. Both of these phenomena which produce inadvertent charging of the gate after it has been severed from the word line, produce unpredictable conduction problems which are not solved by the prior art techniques such as that disclosed by Deliduka. Finally, coupling of stray electric fields can cause accumulation of charge on the floating gate which needs a discharge path.